Cmos Transistor Designs with Magic VLSI- Part 2: D Latch

Here the layout of D Latch

Then you need to modify your netlist as(for detailed information click)

* C:\Program Files (x86)\LTC\LTspiceIV\Draft1.asc

* SPICE3 file created from hwk2.ext - technology: scmos

.model NMOS NMOS

.model PMOS PMOS

M1000 a_n51_n81# invclk D w_n68_n21# PMOS w=24 l=2

+ ad=192 pd=64 as=144 ps=60

M1001 a_n41_n81# clk a_n51_n81# w_n68_n21# PMOS w=24 l=2

+ ad=432 pd=180 as=0 ps=0

M1002 VDD a_n51_n81# a_n29_n81# w_n68_n21# PMOS w=24 l=2

+ ad=384 pd=128 as=144 ps=60

M1003 a_n41_n81# a_n29_n81# VDD w_n68_n21# PMOS w=24 l=2

+ ad=0 pd=0 as=0 ps=0

M1004 a_n51_n81# clk D Gnd NMOS w=12 l=2

+ ad=96 pd=40 as=72 ps=36

M1005 a_n41_n81# invclk a_n51_n81# Gnd NMOS w=12 l=2

+ ad=216 pd=108 as=0 ps=0

M1006 GND a_n51_n81# a_n29_n81# Gnd NMOS w=12 l=2

+ ad=192 pd=80 as=72 ps=36

M1007 a_n41_n81# a_n29_n81# GND Gnd NMOS w=12 l=2

+ ad=0 pd=0 as=0 ps=0

M1008 a_15_n81# clk a_n41_n81# w_n68_n21# PMOS w=24 l=2

+ ad=192 pd=64 as=0 ps=0

M1009 Q invclk a_15_n81# w_n68_n21# PMOS w=24 l=2

+ ad=288 pd=120 as=0 ps=0

M1010 VDD a_15_n81# a_37_n81# w_n68_n21# PMOS w=24 l=2

+ ad=0 pd=0 as=144 ps=60

M1011 Q a_37_n81# VDD w_n68_n21# PMOS w=24 l=2

+ ad=0 pd=0 as=0 ps=0

M1012 a_15_n81# invclk a_n41_n81# Gnd NMOS w=12 l=2

+ ad=96 pd=40 as=0 ps=0

M1013 Q clk a_15_n81# Gnd NMOS w=12 l=2

+ ad=144 pd=72 as=0 ps=0

M1014 GND a_15_n81# a_37_n81# Gnd NMOS w=12 l=2

+ ad=0 pd=0 as=72 ps=36

M1015 Q a_37_n81# GND Gnd NMOS w=12 l=2

+ ad=0 pd=0 as=0 ps=0

C0 w_n68_n21# clk 18.7fF

C1 w_n68_n21# a_n29_n81# 5.3fF

C2 w_n68_n21# a_n51_n81# 5.3fF

C3 invclk w_n68_n21# 18.5fF

C4 w_n68_n21# a_37_n81# 5.3fF

C5 w_n68_n21# a_n41_n81# 5.1fF

C6 w_n68_n21# a_15_n81# 5.3fF

C7 w_n68_n21# VDD 3.0fF

C8 w_n68_n21# Q 3.4fF

C9 Q gnd! 26.8fF

C10 a_37_n81# gnd! 23.7fF

C11 a_15_n81# gnd! 37.8fF

C12 VDD gnd! 51.9fF

C13 a_n41_n81# gnd! 35.4fF

C14 a_n29_n81# gnd! 24.0fF

C15 a_n51_n81# gnd! 39.5fF

C16 invclk gnd! 106.0fF

C17 clk gnd! 115.4fF

V1 clk 0 PULSE(0 5 0 0 0 0.00000005 0.00000001 10)

V2 invclk 0 PULSE(0 5 0.00000005 0 0 0.00000001 0.0000001 10)

V3 D 0 PULSE(0 5 0.000000025 0 0 0.00000005 0.0000001 100)

V4 Vdd 0 5

.tran 0.000001

.backanno

.end

Results;